VLSI Test Principles and Architectures: Design for Testability
Laung-Terng Wang (SynTest Technologies, Inc., Sunnyvale, CA, USA),Cheng-Wen Wu (National Tsing Hua University, Hsinchu, Taiwan.),Xiaoqing Wen (Kyushu Institute of Technology, Fukuoka, Japan.)
VLSI Test Principles and Architectures: Design for Testability
Laung-Terng Wang (SynTest Technologies, Inc., Sunnyvale, CA, USA),Cheng-Wen Wu (National Tsing Hua University, Hsinchu, Taiwan.),Xiaoqing Wen (Kyushu Institute of Technology, Fukuoka, Japan.)
7 ½ X 9 ¼ in Chapter 1
Introduction Chapter 2
Design for Testability
Chapter 3
Logic and Fault Simulation
Chapt er 4
Test Generation
Chapter 5
Logic Built-In Self-Tes t Chapter 6
Test Compression Chapter 7
Log ic Diagnosis Chapter 8
Memory Testing and Built-In Self-T est Chapter 9
Memory Diagnosis and Built-In Self-RepairChapter 10
Boundary Scan and Core-Based Testing Chapter 11
Analog and Mixed-Signal Testing Chapter 12
Test Technology Trends in the Nanometer Age concepts.
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