Design Rules in a Semiconductor Foundry

Nowadays over 50% of the integrated circuits are manufactured at wafer foundries. This book presents a foundry-integrated perspective of the field and is a comprehensive and up-to-date manual designed to serve process, device, layout, and design engineers. It includes chapters carefully selected to cover topics relevant for them to deal with their work. The book provides insight into the different types of design rules (DRs) and considerations for setting new DRs. It includes isolation, gate patterning, S/D, contacts, metal lines, MOL, air gaps, and so on. It explains in detail the layout rules needed to support advanced planarization processes, different types of dummies, and related utilities as well as presents a large set of guidelines and layout-aware modeling for RF CMOS and analog modules. It discusses the layout DRs for different mobility enhancement techniques and their related modeling, listing many of the dedicated rules for static random-access memory (SRAM), embedded polyfuse (ePF), and LogicNVM. Alongside the cookbook description, it provides the setting and calibration of the process parameters set and describes the 28~20 nm planar MOSFET process flow for low-power and high-performance mobile applications in a step-by-step manner. It also includes FEOL and BEOL physical and environmental test for qualifications together with automotive qualification and design for automotive (DfA). Written for the professionals, the book belongs to the bookshelf of microelectronic discipline experts.