Optimizing Compilers for Modern Architectures: A Dependence-based Approach

7 3/8 X 9 ¼ in Preface

Chapter 1 - Compiler Challenges for High-Performance Architectures < BR id=‘CRLF’>

1.1 Overview and Goals

1.2 Pipelining

1.2.1 Pip elined Instruction Units

1.2.2 Pipelined Exe cution Units

1.2.3 Parallel Functional Units

1.2.4 Compiling for Scalar Pipelines

1.3 Vector Instructions

1.3.1 Vector Hardware Overview

1.3.2 Compil ing for Vector Pipelines

1.4 Superscalar and VLIW Processors

1.4.1 Multiple-Issue Instruc tion Units

1.4.2 Compiling for Multiple-Issu e Processors

1.5 Processor Parallelism

1.5.1 Overview of Processor Parallelism

1.5.2 Compiling for Asynchronous Parallelism

1.6 Memory Hierarchy

1.6.1