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On behalf of the organizing committee, we are delighted to welcome you to the 2018 ACM International Symposium on Physical Design (ISPD), held at Seaside, California. Continuing the great tradition established by its twenty-six predecessors, which includes a series of five ACM/SIGDA Physical Design Workshops held intermittently in 1987-1996 and twenty one editions of ISPD in the current form since 1997. The 2018 ISPD provides a premier forum to present leading-edge research results, exchange ideas, and promote research on critical areas related to the physical design of VLSI and other related systems.
The regular papers in the ISPD 2018 program were selected after a rigorous, month-long, double-blind review process and a face-to-face meeting by the Technical Program Committee (TPC) members. The papers selected exhibit latest advancements in a variety of topics in physical design, including emerging challenges for current and future process technologies, FPGA architectures, placement, detailed routing, and application of machine-learning based techniques to physical design.
The ISPD 2018 program is complemented by two keynote addresses, eleven invited talks and a tribute session, all of which are delivered by distinguished researchers from both industry and academia. On Monday morning, Dr. Anthony Hill, fellow of Texas Instruments, Inc., will talk about challenges and opportunities in automotive, industrial, and IoT Physical Design. In the second keynote on Tuesday, Andreas Olofsson, DARPA’s Microsystems Technology Office Program Manager, will discuss the next generation of silicon compilers. A commemorative session on Tuesday afternoon will pay tribute to Professor Te Chiang Hu. His collaborators will share with us Dr. Hu’s exceptional contributions to research in physical design and VLSI applications, including his influential work on trees, flows, and networks. There will be other invited talks interspersed with the presentations of the regular papers. The topics of the invited papers range from advanced FPGA applications, high-speed processor design, logic computation, machine learning in EDA, interconnect optimization, to electromigration-aware physical design.
Since 2005, the ISPD has organized highly competitive contests to promote and advance research in placement, global routing, clock network synthesis, discrete gate sizing, and detailed routingdriven placement. The contest this year, organized by Cadence, focuses on detailed routing. Continuing the tradition of all the past contests, a new large-scale real-world benchmark suite for detailed routing has been specified using LEF/DEF and will be released in the ISPD website (http: //www.ispd.cc). The contest evaluates the routing quality and the ability to connect all the nets of a design without design rule violations. It is expected to lead and motivate more research and contributions on the detailed routing of large integrated circuits.
