This title was conceived as a manual for the design of fully integrated S fractional-N frequency synthesizers in CMOS with a focus on achieving a high spectral purity, that is, low-phase-noise and high spurious suppression. Fractional-N design is elaborated from specification derivation up to architectural and building block level and down to circuit level. CMOS Fractional-N Synthesizers starts with a comprehensive introduction to general frequency synthesis. Different architectures and synthesizer building blocks are discussed with their relative importance on synthesizer specifications. The process of synthesizer specification derivation is illustrated with the DCS-1800 standard as a general test case. The book tackles the design of fractional-N synthesizers in CMOS on circuit level as well as system level. The circuit level focuses on high-speed prescaler design up to 12 GHz in CMOS and on fully integrated, low-phase-noise LC-VCO design. High-Q inductor integration and simulation in CMOS is elaborated and flicker noise minimization techniques are presented, ranging from bias point choice to noise filtering techniques. On a higher level, a systematic design strategy has been developed that trades off all noise contributions and fast dynamics for integrated capacitance (area). Moreover, a theoretical S phase noise analysis is presented, extended with a fast non-linear analysis method to accurately predict the influence of PLL non-linearities on the spectral purity of the S fractional-N frequency synthesizers. CMOS Fractional-N Synthesizers covers the total design flow of monolithic CMOS fractional-N synthesizers with high spectral purity while providing insight in the most critical issues of monolithic fractional-N synthesis. All material is experimentally verified with several CMOS implementations, with ultimately a monolithic CMOS S-controlled fractional-N synthesizer, which was part of a CMOS DCS-1800 transceiver front-end.