Behavioral Synthesis and Component Reuse with VHDL

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Improvement in the quality of integrated circuit designs and a designer’s productivity can be achieved by a combination of two factors: using more structured design methodologies for extensive reuse of existing components and subsystems; and providing higher level design tools allowing to start from a higher level of abstraction. After the success and the widespread acceptance of logic and RTL synthesis, the next step is behavioural synthesis, commonly called architectural or high-level synthesis. This text provides methods and techniques for VHDL based behavioural synthesis and component reuse. The aim is to develop VHDL modeling strategies for emerging behavioural synthesis tools. Special attention is given to structured and modular design methods allowing hierarchical behavioural specification and design reuse.