High-Level System Modeling: Specification Languages

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The process of modelling hardware involves a certain duality: a model may specify and represent the desires and constraints of the designer, or it may imitate something that already exists, and can end in simulation or documentation. One of the main qualities of a specification formalism is its ability to ignore issues that do not belong to this level. Such formalisms are obviously intended for the first stages of a design, but can also be used in the process of redesign. Having a proper level of description thus avoids two symmetric problems: overspecification, which would introduce new instances of the hardware constraints that were only meaningful to the previous ones; and underspecification, which would lead to unnecessary work and sometimes to starting again from scratch. Describing recent progress in specification formalisms in electronic design, this work provides an overview of object-oriented methodologies. It goes on to highlight several formalisms such as VSPEC, ESTELLE, SDL and LOTOS with methods that map their semantics to simulatable or synthesizable VHDL.