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Integrated Circuit Defect-Sensitivity: Theory and Computational Models
Hardback

Integrated Circuit Defect-Sensitivity: Theory and Computational Models

$276.99
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This title is printed to order. This book may have been self-published. If so, we cannot guarantee the quality of the content. In the main most books will have gone through the editing process however some may not. We therefore suggest that you be aware of this before ordering this book. If in doubt check either the author or publisher’s details as we are unable to accept any returns unless they are faulty. Please contact us if you have any questions.

Spot defects are random phenomena present in every fabrication line. As technological processes mature towards submicron features, the effect of these defects on the functional and parametric behaviour of the IC becomes crucial. This work reviews the importance of a defect-sensitivity analysis in contemporary VLSI design processes. The modelling of defects in microelectronics technologies is revised from a set theoretical approach as well as from a practical point of view. This way of handling the material introduces the reader step by step to critical area analysis through the construction of formal mathematical models. The rigorous formalism developed in the book is necessary to study the construction of deterministic algorithms for layout defect exploration. Without this basis, it would be impossible to scan layouts in the order of 1,000,000 objects, or more, in a reasonable time. The theoretical component of this book is complemented with a set of practical case studies for fault extraction, yield prediction and IC defect-sensitivity evaluation. These case studies emphasize the fact that by suing appropriate formulae combining statistical data with the computed defect-sensitivity, an estimate of the IC’s defect tolerance can be obtained at the end of the respective production line. The case studies include a vast range of illustrations depicting critical areas. Examples range from highlighting their geometical nature as a function of the defect size to more specific situations highlighting layout regions where faults may occur. In addition to the visualization of critical areas, numerical data in the form of tables, graphs and histograms are provided for quantification purposes. More than that, ever smarter, defect-tolerant design strategies have to be devised to attain high yields. Obviously, the work presented in the book is not definitive, and more research will always be useful to advance the field of CAD for manufacturability. This is, of course, one of the challenges imposed by the ever-changing nature of microelectronic technologies. CAD developers and yield practitioners from academia and industry should find that this book lays the foundations for further pioneering work.

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MORE INFO
Format
Hardback
Publisher
Springer
Country
NL
Date
31 December 1992
Pages
167
ISBN
9780792393061

This title is printed to order. This book may have been self-published. If so, we cannot guarantee the quality of the content. In the main most books will have gone through the editing process however some may not. We therefore suggest that you be aware of this before ordering this book. If in doubt check either the author or publisher’s details as we are unable to accept any returns unless they are faulty. Please contact us if you have any questions.

Spot defects are random phenomena present in every fabrication line. As technological processes mature towards submicron features, the effect of these defects on the functional and parametric behaviour of the IC becomes crucial. This work reviews the importance of a defect-sensitivity analysis in contemporary VLSI design processes. The modelling of defects in microelectronics technologies is revised from a set theoretical approach as well as from a practical point of view. This way of handling the material introduces the reader step by step to critical area analysis through the construction of formal mathematical models. The rigorous formalism developed in the book is necessary to study the construction of deterministic algorithms for layout defect exploration. Without this basis, it would be impossible to scan layouts in the order of 1,000,000 objects, or more, in a reasonable time. The theoretical component of this book is complemented with a set of practical case studies for fault extraction, yield prediction and IC defect-sensitivity evaluation. These case studies emphasize the fact that by suing appropriate formulae combining statistical data with the computed defect-sensitivity, an estimate of the IC’s defect tolerance can be obtained at the end of the respective production line. The case studies include a vast range of illustrations depicting critical areas. Examples range from highlighting their geometical nature as a function of the defect size to more specific situations highlighting layout regions where faults may occur. In addition to the visualization of critical areas, numerical data in the form of tables, graphs and histograms are provided for quantification purposes. More than that, ever smarter, defect-tolerant design strategies have to be devised to attain high yields. Obviously, the work presented in the book is not definitive, and more research will always be useful to advance the field of CAD for manufacturability. This is, of course, one of the challenges imposed by the ever-changing nature of microelectronic technologies. CAD developers and yield practitioners from academia and industry should find that this book lays the foundations for further pioneering work.

Read More
Format
Hardback
Publisher
Springer
Country
NL
Date
31 December 1992
Pages
167
ISBN
9780792393061