The Verilog hardware description language is widely used in both industry and academia for the description of digital systems. The language supports the early conceptual stages of design with its behavioural level of abstraction and the later implementation stages with its structural level of abstraction. The language provides hierarchical constructs, allowing the designer to control the complexity of description. This work takes a tutorial approach to presenting the language. It starts with a tutorial introduction which presents the major features of the language by example. It then continues with a more complete discussion of the language constructs. Numerous examples are provided to allow the reader to learn by example. Finally, a formal description of the language is provided in the Appendix. Overall, the presentation balances a learn-by-example style with a definitive discussion of the language. It assumes a knowledge of introductory logic design and software programming. As such, the book is of use to practicing integrated circuit design engineers, and undergraduate and graduate electrical or computer engineering students. The tutorial introduction provides enough information for students in an introductory logic design course to make simple use of logic simulation as part of their laboratory experience. The rest of the book could then be used in upper level logic design and architecture courses. Included in the book is a disk that contains a DOS version of the VeriWell Verilog simulator as well as examples from the book. The examples can be simulated, modified and re-simulated. The simulator can also be used to solve the exercises.