CHARM 97 is the ninth in a series of working conferences devoted to the development and use of formal techniques in digital hardware design and verification. This series is held in collaboration with IFIP WG 10.5. Previous meetings were held in Europe every other year. Formal verification is increasingly recognized as an appropriate tool for design acceptance and for detecting design errors and specification ambiguities. The validation of functional and timing behaviour is a major bottleneck in current VLSI design systems. Once an academic area, formal design and verification techniques are attracting serious attention from industry. Given this increased activity, the series aims to attract researchers and users from both communities. This working conference focuses on the integration of verification technologies, identifying ideal subdomains of application for each and on the possibility of creating hybrid verification tools and approaches.